The present technology relates to a circuit, particularly, to a circuit that generates timing by utilizing charging and discharging to and from a capacitor using a current source.
Various types of soft start-up circuits according to the related art are known (see, for example, Hirokazu Tsujimoto and Tetsuo Tateishi, “SOFT STARTING REFERENCE VOLTAGE CIRCUIT”, U.S. Pat. No. 6,348,833, Kabushiki Kaisya Toyoda Jidoshokki Seisakusyo, 2002 (Patent Literature 1), Chun-Yu Hsieh, Yung-Chun Chuang, and Ke-Horng Chen, “A Novel Precise Step-Shaped Soft-Start Technique for Integrated DC-DC Converter”, 14th IEEE International Conference on Electronics, Circuits and Systems, pp 771-774, 2007 (Non-Patent Literature 1), and Ke-Horng Chen, Chia-Jung Chang and Te-Hsien Liu, “Bidirectional Current-Mode Capacitor Multipliers for On-Chip Compensation”, IEEE Transactions on Power Electronics, Vol. 23, 2008, pp 180-188 (Non-Patent Literature 2)). FIG. 15 is a diagram illustrating an example power supply circuit including a soft start-up circuit, and FIG. 16 is a timing chart for explaining the operation of the power supply circuit illustrated in FIG. 15. The power supply circuit 1 illustrated in FIG. 15 is a step-down DC-DC converter in voltage control mode, and includes a DC power supply voltage B, switching elements M1, M2, an inductor L, an output capacitor C, a feedback control circuit FB, and a soft start-up circuit SS.
One end of the inductor L is connected to the positive terminal of the power supply voltage B via the switching element M1 as well as to the ground via the switching element M2. The other end of the inductor L is connected to a load as well as to the ground via the output capacitor C.
The switching element M1 is a P-channel electric field effect transistor (hereinafter referred to as a PFET), and when the switching element M1 is switched from off to on, magnetic energy is stored in the inductor L, and a current, which is smoothed by the inductor L and the capacitor C, is supplied to the load.
The switching element M2 is an N-channel electric field effect transistor (hereinafter referred to as a NFET), and when the switching element M2 is switched from off to on, the magnetic energy stored in the inductor L flows as a current through the load via the switching element M2 and is discharged, the current being smoothed by the inductor L and the capacitor C. It should be noted that the switching element M2 may be configured with a commutation diode.
The switching elements M1, M2 receive inputs of PWM control signals at their control terminals from the driver circuit Dry described later, the PWM control signals having on/off states inverted to each other. That is, when the switching element M1 is on, the switching element M2 is off, and when the switching element M1 is off, the switching element M2 is on. In this manner, constant voltage control can be performed according to a duty ratio of the PWM control signals.
The feedback control circuit FB includes an error amplifier EA, a comparator Comp, a flip-flop FF, and the driver circuit Drv, and is configured to control on/off of the switching elements M1, M2 so that an output voltage V0 converges to a target voltage.
The error amplifier EA detects an error between the output voltage and the target voltage, and outputs an error voltage Ve. Specifically, the error amplifier EA receives inputs of a voltage bV0 and a reference voltage Vref, and outputs a voltage as the error voltage Ve according to the difference between the voltage bV0 and the reference voltage Vref, the voltage bV0 being obtained by dividing the output voltage V0 of the power supply circuit 1 into a predetermined ratio, the reference voltage Vref indicating the target voltage of the voltage Vb0.
The comparator Comp generates a switching signal to be outputted to the driver circuit Drv. Specifically, the comparator Comp receives inputs of the error voltage Ve and a ramp wave Vramp which is a saw-tooth triangular wave inputted from a triangular wave generation circuit, and outputs a signal of positive logic (high level) when the error voltage Ve is higher than the lamp signal Vramp, or outputs a signal of negative logic (low level) when the error voltage Ve is lower than or equal to the ramp signal Vramp. That is, a PWM signal Spwm having a frequency according to the period of the ramp wave Vramp is outputted.
The flip-flop FF receives inputs of the PWM signal Spwm and a clock signal CK at reset terminal R and set terminal S, respectively, and outputs a PWM signal equivalent to the PWM signal Spwm to the driver circuit Dry only when the clock signal CK is being inputted.
When positive logic (high level) is inputted, the driver circuit Dry turns on the switching element M1 and turns off the switching element M2, whereas when negative logic (low level) is inputted, the driver circuit Dry turns off the switching element M1 and turns on the switching element M2.
Thus, the on/off ratio of the switching element M1 and the switching element M2 is controlled as follows: when the output voltage V0 is lower than the target voltage, the on-proportion of the switching element M1 and the off-proportion of the switching element M2 are increased, whereas when the output voltage V0 is higher than the target voltage, the off-proportion of the switching element M1 and the on-proportion of the switching element M2 are increased. As a consequence, on/off of the switching elements M1, M2 is controlled so that the output voltage V0 converges to the target voltage.
In the case where a desired reference voltage Vref is directly inputted to the error amplifier without providing the soft start-up circuit SS, when the power supply is activated, a rush current flows due to an abrupt rise of the output voltage. The rush current that occurs at the time of activation of the power supply is caused by a current that is for supplying charging current to the output capacitor
Specifically, when voltage bV0 corresponding to the output voltage V0 and the reference voltage Vref are inputted to the error amplifier at the time of activation of the power supply 1, the error voltage Ve outputted by the error amplifier EA is increased to nearly power supply voltage Vg.
At this point, the output of the comparator Comp is in a low level state, and thus the switching element M1 is turned on, and this state continues until all capacitors connected to the power source line are charged to a set voltage.
An increasing amount of current is continued to be supplied from a power supply circuit and/or a battery in a previous stage that supply power to the power supply circuit 1, which eventually causes an over current state, and a problem such as breakdown of a power transistor (such as the transistor elements M1, M2) and/or the inductor L may occur.
The capacitance of the output capacitor is decreasing every year due to an increase in switching frequency, and so effect of large capacitance is decreasing. However, many power supply circuits still need large-capacitance output capacitors, and in some cases, not only output capacitors but also huge capacitors are installed in a power line as a measure against momentary power failure. Therefore, at the time of activation of such a power supply circuit, it is necessary to charge all capacitors connected to the power line from 0V to the set voltage.
In order to avoid such a problem, it is preferable to reduce the charging current to the output capacitors. To cope with this, the power supply circuit 1 including a DC-DC converter is provided with a soft start-up circuit SS (see, for example, Patent Literature 1 and Non-Patent Literature 1, 2) that controls charging current to a capacitor to be lower than a certain level by delaying the increasing rate of the output voltage, thereby reducing rush current and/or overshoot which occurs due to an input at the time of activation of the power supply circuit 1.